The semiconductor-on-insulator or silicon-on-insulator (SOI) technology has been recognized to have promising applications in high voltage applications, high radiation applications, and smart power applications where high current and voltage devices and low voltage and current devices are built on the same wafer. In the SOI technology devices are completely surrounded or isolated by an insulator rather than a pn junction as in conventional devices.
Current viable SOI fabrication processes include wafer bonding in which two oxidized silicon wafers are fused together. One of the outer silicon surfaces is either chemically polished, etched or mechanically lapped to a desired thickness. One disadvantage associated with wafer bonding is the limitation on the minimum thickness that can be achieved and the uniformity of that thickness across the wafer. In addition, wafer bonding is acutely susceptible to voids created at the bonding surface by the presence of particulates.
An alternative to the wafer bonding process is commonly known as SIMOX (Separation by IMplanted OXygen). In SIMOX, a buried layer of SiO.sub.2 or silicon oxide is created by implanting oxygen into silicon. The technique requires a high dose of oxygen ions accelerated to high kinetic energies directed into the silicon wafer and implanted at a sufficient depth within the silicon. A subsequent anneal step allows the implanted oxygen ions to complete the reaction with the silicon to form a continuous layer of buried stoichiometric silicon oxide. As a result, a buried oxide layer lies beneath a surface silicon layer of appropriate thickness, and a bulk silicon layer lies beneath the oxide layer. However, this process creates undesirable silicon islands or inclusions in the buried oxide layer near the bulk silicon interface. The presence of silicon inclusions in the buried oxide causes a decrease in the dielectric breakdown voltage of the resultant devices. Furthermore, the silicon inclusions may also trap radiation induced carriers, which effectively decreases the radiation hardness of resultant circuits.
Two methods for eliminating undesirable silicon inclusions are known in the industry. The first method involves multiple implantation and anneal steps. Although successful, this method introduces additional fabrication cost and time into the SIMOX process. The second method involves increasing the ion implant energy. During implantation, wafer heating is normally provided by the implantation beam energy. Lower energy results in a lower wafer temperature during implantation. The normal beam energy is also the practical upper limit for production ion implantation. Because approximately 600.degree. C. wafer temperature is required to preserve surface silicon crystallinity, the variation in implant energy directly affects the wafer quality. Therefore, additional temperature and implantation energy monitoring and compensation methods must be considered and employed.
Accordingly, it is desirable to provide an SOI method for forming a buried oxide layer in silicon that is essentially free of silicon inclusions. In addition, it is desirable that this method not require processing steps dissimilar to conventional IC manufacturing steps for cost and time considerations.